A memory cell in an integrated circuit (IC) may include a transfer device such as a transistor and an associated capacitor. The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals. One type of transistor is known as the field effect transistor (FET).
The capacitor, which is typically formed in a portion of a trench, consists of a pair of conductive plates (electrodes), which are separated from each other by a node dielectric material. Information or data is stored in the memory cell in the form of charge accumulated on the capacitor. Since capacitors leak charge (generally, a capacitor is only useful for temporarily storing an electrical charge), the information (data) eventually fades unless the capacitor charge is refreshed (read and re-written) periodically, such as every 64 ms (milliseconds).
DRAM (eDRAM)
Generally, the DRAM cells discussed herein comprise a capacitor formed in a deep trench (DT) in a substrate, and an “access transistor” formed on the surface of the substrate adjacent and atop the capacitor. The capacitor (“DT capacitor”) generally comprises a first conductive electrode called the “buried plate” which is a heavily doped region of the substrate surrounding the trench, a thin layer of insulating material such as oxide lining the trench, and a second conductive electrode such as a heavily doped polycrystalline plug (or “node”) disposed within the trench. The transistor may comprise a FET having one of its source/drain (S/D) terminals connected to (or an extension of) the second electrode (node) of the capacitor.
FIG. 1 illustrates a DRAM cell 100 of the prior art, generally comprising an access transistor and an associated cell capacitor. The DRAM cell is generally formed, as follows.
Beginning with a semiconductor substrate 102, a deep trench (DT) 110 is formed, extending into the substrate 102, from a top (as viewed) surface thereof. The substrate 102 may comprise a SOI substrate having a layer 106 of silicon (SOI) on top of an insulating layer 104 which is atop the underlying silicon substrate 102. The insulating layer 104 typically comprises buried oxide (BOX). The deep trench (DT) 110 is for forming the cell capacitor (or “DT capacitor”), as follows. The trench 110 may have a width of about 50 nm to 200 nm and a depth of 1000 nm to 10000 nm, by way of example.
The cell capacitor generally comprises a first conductor called the “buried plate” which is a heavily doped region 112 of the substrate surrounding the trench 110, a thin layer 114 of insulating material lining the trench 110, and a second conductor 116 such as a heavily doped polycrystalline plug (or “node”, “DT poly”) disposed within the trench 110. A cell transistor (“access transistor”) 120 may comprise a FET having one of its source/drain (S/D) terminals connected to (or an extension of) the second conductor (node) of the capacitor, as follows.
The FET 120 comprises two spaced-apart diffusions, 122 and 124, within the surface of the substrate 102—one of which will serve as the “source” and the other of which will serve as the “drain” (D) of the transistor 120. The space between the two diffusion areas is called the “channel” (and is approximately where the legend “SOI” appears). A thin dielectric layer 126 is disposed on the substrate above the channel, and a “gate” structure (G) 128 is disposed over the dielectric layer 126, thus also atop the channel. (The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”.) The gate 128 may be a portion of an elongate wordline (WL).
In modern CMOS technology, shallow trench isolation (STI) is commonly used to isolate one (or more) transistors from other transistors, for both logic and memory. As shown in FIG. 1, a shallow trench 132 may be formed, surrounding the access transistor 120 (only one side of the transistor is shown). Note that the trench 132 extends over the DT (node) poly 116, a top portion of which is adjacent the drain (D) of the transistor 120. Therefore, the trench 132 is less deep (thinner) over the DT poly 116 and immediately adjacent the drain (D) of the transistor 120, and may be deeper (thicker) further from the drain (D) of the transistor 120 (and, as shown, over top portion of the DT poly 116 which is distal from (not immediately adjacent to) the drain (D) of the transistor 120.
The STI trench 132 may be filled with an insulating material, such as oxide (STI oxide) 134. Because of the thin/thick trench geometry which has been described, the STI oxide will exhibit a thin portion 134a where it is proximal (adjacent to) the drain (D) of the transistor 120, and a thicker portion where it is distal from (not immediately adjacent to) the drain (D) of the transistor 120.
As illustrated in FIG. 2, the deep trench (DT) may be “bottle-shaped”, such that it is wider in the substrate under the BOX, and a thinner bottleneck portion of the trench extends through the BOX (and overlying SOI, not shown). The deep trench is typically filled with poly (DT Poly, compare 116), there is a lining of insulator (compare 114), and the trench is surrounded by the buried plate (compare 112). This forms deep trench capacitor, which is generally not limited to SOI.
SOI Substrates
Silicon on insulator technology (SOI) refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or (less commonly) sapphire. The choice of insulator depends largely on intended application, with sapphire being used for radiation-sensitive applications and silicon oxide preferred for improved performance and diminished short channel effects in microelectronics devices. The precise thickness of the insulating layer and topmost silicon layer also vary widely with the intended application.
SiO2-based SOI substrates (or wafers) can be produced by several methods:                SIMOX—Separation by IMplantation of OXygen—uses an oxygen ion beam implantation process followed by high temperature annealing to create a buried SiO2 layer.        Wafer Bonding—the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer.        Seed methods—wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying substrate.Related Patents and Publications        
U.S. Pat. No. 3,387,286 (IBM; 1968) discloses field effect transistor memory. The memory is formed of an array of memory cells controlled for reading and writing by word lines and bit lines which are connected to the cells. Each cell is formed using a single FET and a single capacitor. The gate electrode of the FET is connected to the word line, the source terminal is connected to the bitline, and the drain terminal is connected to one of the (two) electrodes of the capacitor. The other electrode of the capacitor is connected to a reference potential. Information is stored by charging the capacitor through the transistor, and information is read out by discharging the capacitor through the transistor. During a “write” operation, the wordline which is connected to the gate of the transistor is energized to render the transistor conductive between source and drain. If a “zero” is to be stored, the bitline is not energized and the capacitor is not charged. If a “one” is to be stored, the bitline is energized and the capacitor is charged to substantially the potential (voltage) of the bitline signal. During “read” operations, only the wordline is energized and a signal is transmitted to the bit lie if a “one” has been stored previously (the capacitor is charged). Since the charge on the capacitor leaks off, it is necessary to periodically regenerate the information stored in the memory.
U.S. Pat. No. 6,977,227 (2005), incorporated by reference herein, discloses a method for forming a bottle trench. First, a substrate covered by a photoresist layer is rotated to a specific angle prior to performance of lithography, thereby forming a rectangular opening in the photoresist layer and exposing the substrate, in which edges of the rectangular opening are substantially parallel to the {110} plane of the substrate due to the rotation of the substrate. Next, the exposed substrate is etched to form a trench therein, in which the sidewall surface of the trench is the {110} plane of the substrate. Finally, isotropic etching is performed on the substrate of the lower portion of the trench using an etching shield layer formed on the sidewall of the upper portion of the trench as an etching mask, to form the bottle trench. There is also disclosed a method of fabricating a bottle trench capacitor. As noted in this patent, one method employed to increase capacitance is to widen the lower portion of a trench, thus, increasing the surface area and creating a “bottle shaped” capacitor.
U.S. Pat. No. 7,132,324 (IBM, 2006), incorporated by reference herein, discloses SOI device with different crystallographic orientations. A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having an [010] axis oriented at forty-five degrees with respect to the wafer axis, the two being connected by a layer of bonding insulator; etching a trench through the upper layer and lower substrate; enlarging the lower portion of the trench and converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. An alternative version employs a bonded semiconductor wafer having a lower substrate formed from a (111) crystal structure and the same upper portion. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the lithographic pattern for the active area, in particular a DRAM cell with a vertical transistor.
U.S. Pat. No. 7,087,486 (IBM, 2006), incorporated by reference herein, discloses method for scalable, low-cost polysilicon capacitor in a planar DRAM. Capacitor structures that have increased capacitance without compromising cell area are provided as well as methods for fabricating the same. A first capacitor structure includes insulating material present in holes that are formed in a semiconductor substrate, where the insulating material is thicker on the bottom wall of each capacitor hole as compared to the sidewalls of each hole. In another capacitor structure, deep capacitor holes are provided that have an isolation implant region present beneath each hole.
Glossary
Unless otherwise noted, or as may be evident from the context of their usage, any terms, abbreviations, acronyms or scientific symbols and notations used herein are to be given their ordinary meaning in the technical discipline to which the invention most nearly pertains. The following terms, abbreviations and acronyms may be used throughout the descriptions presented herein and should generally be given the following meaning unless contradicted or elaborated upon by other descriptions set forth herein. Some of the terms set forth below may be registered trademarks®.    anisotropic literally, one directional. An example of an anisotropic process is sunbathing. Only surfaces of the body exposed to (facing in the direction of) the sun become tanned. Anisotropic means “not the same in all directions” or “not isotropic”. See isotropic.    capacitor A capacitor is a two-terminal device (electrical or electronic component) that can store energy in the electric field between a pair of conductive electrodes (called “plates”). The process of storing energy in the capacitor is known as “charging”, and involves electric charges of equal magnitude, but opposite polarity, building up on each plate.    CMP short for chemical-mechanical polishing. CMP is a process, using both chemicals and abrasives, comparable to lapping (analogous to sanding), for removing material from a built up structure. For example, after depositing and etching a number of elements, the top surface of the resulting structure may very uneven, needing to be smoothed (or levelled) out, prior to performing a subsequent process step. Generally, CMP will level out the high spots, leaving a relatively smooth planar surface.    CVD short for chemical vapor deposition. CVD is a chemical process used to produce high-purity, high-performance solid materials. The process is often used in the semiconductor industry to produce thin films. In a typical CVD process, the wafer (substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit. CVD is used to deposit materials in various forms, including: monocrystalline, polycrystalline, amorphous, and epitaxial. These materials include: silicon, oxide, nitride and metals, such as are commonly used in semiconductor fabrication.    deposition Deposition generally refers to the process of applying a material over another material (or the substrate). Chemical vapor deposition (CVD) is a common technique for depositing materials. Other “deposition” techniques, such as for applying resist or glass, may include “spin-on”, which generally involves providing a stream of material to the substrate, while the substrate is spinning, resulting in a relatively thin, flat, evenly-distributed coating of the material on the underlying substrate.    dopant element introduced into semiconductor to establish either p-type (acceptors) or n-type (donors) conductivity; common dopants in silicon: for p-type—boron (B), Indium (In); for n-type—phosphorous (P) arsenic (As), antimony (Sb). Dopants are of two types—“donors” and “acceptors”. N type implants are donors and P type are acceptors.    doping doping is the process of introducing impurities (dopants) into the semiconductor substrate, or elements formed on the semiconductor substrate, and is often performed with a mask (or previously-formed elements in place) so that only certain areas of the substrate will be doped. For example, doping is used to form the source and drain regions of an FET. An ion implanter is typically employed for the actual implantation. An inert carrier gas such as nitrogen is usually used to bring in the impurity source (dopant). Usually in doping, a dopant, a dosage and an energy level are specified and/or a resulting doping level may be specified. A dosage may be specified in the number of atoms per cm2 and an energy level (specified in keV, kilo-electron-volts), resulting in a doping level (concentration in the substrate) of a number of atoms per cm3. The number of atoms is commonly specified in exponential notation, where a number like “3E15” means 3 times 10 to the 15th power, or a “3” followed by 15 zeroes (3,000,000,000,000,000). To put things in perspective, there are about 1E23 (100,000,000,000,000,000,000,000) atoms of hydrogen and oxygen in a cubic centimeter (cm3) of water. An example of doping is implanting with B (boron) with a dosage of between about 1E12 and 1E13 atoms/cm2, and energy of about 40 to 80 keV to produce a doping level of between 1E17 and 1E18 atoms/cm3. (“/cm3” may also be written “cm−3”    DRAM short for dynamic random access memory. DRAM is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Since real capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory. Its advantage over SRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to six transistors in SRAM. This allows DRAM to reach very high density. Like SRAM, it is in the class of volatile memory devices, since it loses its data when the power supply is removed.    eDRAM short for embedded DRAM. eDRAM is a capacitor-based dynamic random access memory usually integrated on the same die or in the same package as the main ASIC or processor, as opposed to external DRAM modules and transistor-based SRAM typically used for caches.    etching etching generally refers to the removal of material from a substrate (or structures formed on the substrate), and is often performed with a mask in place so that material may selectively be removed from certain areas of the substrate, while leaving the material unaffected, in other areas of the substrate. There are generally two categories of etching, (i) wet etch and (ii) dry etch.            Wet etch is performed with a solvent (such as an acid) which may be chosen for its ability to selectively dissolve a given material (such as oxide), while leaving another material (such as polysilicon) relatively intact. This ability to selectively etch given materials is fundamental to many semiconductor fabrication processes. A wet etch will generally etch a homogeneous material (e.g., oxide) isotropically, but a wet etch may also etch single-crystal materials (e.g. silicon wafers) anisotropically.        Dry etch may be performed using a plasma. Plasma systems can operate in several modes by adjusting the parameters of the plasma. Ordinary plasma etching produces energetic free radicals, neutrally charged, that react at the surface of the wafer. Since neutral particles attack the wafer from all angles, this process is isotropic. Ion milling, or sputter etching, bombards the wafer with energetic ions of noble gases which approach the wafer approximately from one direction, and therefore this process is highly anisotropic. Reactive-ion etching (RIE) operates under conditions intermediate between sputter and plasma etching and may be used to produce deep, narrow features, such as STI trenches.            FET short for field effect transistor. The FET is a transistor that relies on an electric field to control the shape and hence the conductivity of a “channel” in a semiconductor material. FETs are sometimes used as voltage-controlled resistors. The terminals of FETs are designated source (S), drain (D) and gate (G).    isotropic literally, identical in all directions. An example of an isotropic process is dissolving a tablet in water. All exposed surfaces of the tablet are uniformly acted upon. (see “anisotropic”)    lithography In lithography (or “photolithography”), a radiation sensitive “resist” coating is formed over one or more layers which are to be treated in some manner, such as to be selectively doped and/or to have a pattern transferred thereto. The resist, which is sometimes referred to as a photoresist, is itself first patterned by exposing it to radiation, where the radiation (selectively) passes through an intervening mask or template containing the pattern. As a result, the exposed or unexposed areas of the resist coating become more or less soluble, depending on the type of photoresist used. A developer is then used to remove the more soluble areas of the resist leaving a patterned resist. The pattered resist can then serve as a mask for the underlying layers which can then be selectively treated, such as to receive dopants and/or to undergo etching, for example.    mask The term “mask” may be given to a layer of material which is applied over an underlying layer of material, and patterned to have openings, so that the underlying layer can be processed where there are openings. After processing the underlying layer, the mask may be removed. Common masking materials are photoresist (resist) and nitride. Nitride is usually considered to be a “hard mask”.    metallization Metallization refers to formation of metal contacts and interconnects in the manufacturing of semiconductor devices. This generally occurs after the devices are completely formed, and ready to be connected with one another. A first level or layer of metallization is usually referred to as “M1”.    nitride commonly used to refer to silicon nitride (chemical formula Si3N4). A dielectric material commonly used in integrated circuit manufacturing. Forms an excellent mask (barrier) against oxidation of silicon (Si). Nitride is commonly used as a hard mask (HM).    n-type semiconductor in which concentration of electrons is higher than the concentration of “holes”. See p-type.    oxide commonly used to refer to silicon dioxide (SiO2). Also known as silica. SiO2 is the most common insulator in semiconductor device technology, particularly in silicon MOS/CMOS where it is used as a gate dielectric (gate oxide); high quality films are obtained by thermal oxidation of silicon. Thermal SiO2 forms a smooth, low-defect interface with Si, and can be also readily deposited by CVD. Oxide may also be used to fill STI trenches, form spacer structures, and as an inter-level dielectric, for example.    plasma etching Plasma etching refers to dry etching in which semiconductor wafer is immersed in plasma containing etching species; chemical etching reaction is taking place at the same rate in any direction, i.e. etching is isotropic; can be very selective; used in those applications in which directionality (anisotropy) of etching in not required, e.g. in resist stripping.    poly short for polycrystalline silicon (Si). Heavily doped poly Si is commonly used as a gate contact in silicon MOS and CMOS devices.    p-type semiconductor in which concentration of “holes” is higher than the concentration of electrons. See n-type. Examples of p-type silicon include silicon doped (enhanced) with boron (B), Indium (In) and the like.    resist short for photoresist also abbreviated “PR”. Photoresist is often used as a masking material in photolithographic processes to reproduce either a positive or a negative image on a structure, prior to etching (removal of material which is not masked). PR is usually washed off after having served its purpose as a masking material.    RIE short for Reactive Ion Etching. RIE is a variation of plasma etching in which during etching, the semiconductor wafer is placed on an RF powered electrode. The plasma is generated under low pressure (vacuum) by an electromagnetic field. It uses chemically reactive plasma to remove material deposited on wafers. High-energy ions from the plasma attack the wafer surface and react with it. The wafer takes on potential which accelerates etching species extracted from plasma toward the etched surface. A chemical etching reaction is preferentially taking place in the direction normal to the surface—in other words, etching is more anisotropic than in plasma etching but is less selective. RIE typically leaves the etched surface damaged. RIE is a very common etching mode in semiconductor manufacturing.    Si Silicon, a semiconductor.    SI units The International System of Units (abbreviated SI from the French Le Systéme international d'unités) is the modern form of the metric system and is generally a system devised around the convenience of the number 10. It is the world's most widely used system of units, both in everyday commerce and in science. The SI system of units consists of a set of units together with a set of prefixes. There are seven “base units”, which are meter (abbreviated “m”, for length), kilogram (abbreviated “kg”, for mass), second (abbreviated “s”, for time), Ampere (abbreviated “A”, for electric current), Kelvin (abbreviated “K”, for thermodynamic temperature), mole (abbreviated “mol”, for the amount of a substance), and candela (abbreviated “cd”, for luminous intensity). A prefix may be added to the units to produce a multiple of the original unit. All multiples are integer powers of ten. For example, “kilo” denotes a multiple of a thousand and “milli” denotes a multiple of one-thousandth. Hence there are one thousand millimeters to the meter and one thousand meters to the kilometer.    SOI short for silicon-on-insulator. Silicon on insulator (SOI) technology refers to the use of a layered silicon-insulator-silicon substrate in place of a conventional silicon substrate in semiconductor manufacturing, especially microelectronics. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or (less commonly) sapphire.    Substrate typically a wafer, of semiconductor material such as silicon, germanium, silicon germanium, silicon carbide, and those consisting essentially of III-V compound semiconductors such as GaAs, II-VI compound semiconductors such as ZnSe. A substrate may also comprise an organic semiconductor or a layered semiconductor such as, for example, Si/SiGe, a silicon-on-insulator or a SiGe-on-insulator. A portion or entire semiconductor substrate may be amorphous, polycrystalline, or monocrystalline. A substrate is often covered by an oxide layer (sometimes referred to as a “pad oxide layer”). Pad oxide is usually relatively thin, e.g., in the range of about 50 to about 500 Angstroms (5-50 nm), and can be formed, for example, by thermal oxidation of the substrate. Pad oxide may also be prepared by other methods. For example, silicon dioxide or reactive precursors like silane could be deposited by chemical vapor deposition (CVD). A nitride layer (sometimes referred to as a “pad nitride layer”) may be formed to protect the pad oxide and the underlying substrate during various processing steps. It usually has a thickness in the range of about 100 Angstroms to about 6000 Angstroms (10-600 nm), such as in the range of about 1500 Angstroms to about 3000 Angstroms (150-300 nm). Conventional means can be used to apply the pad nitride, such as chemical vapor deposition (CVD).    Transistor A transistor is a semiconductor device, commonly used as an amplifier or an electrically controlled switch. The transistor is the fundamental building block of the circuitry in computers, cellular phones, and all other modern electronic devices. Because of its fast response and accuracy, the transistor is used in a wide variety of digital and analog functions, including amplification, switching, voltage regulation, signal modulation, and oscillators. Transistors may be packaged individually or as part of an integrated circuit, some with over a billion transistors in a very small area. See FET.    Units of Length Various units of length may be used herein, as follows:            meter (m) A meter is the SI unit of length, slightly longer than a yard.                    1 meter=˜39 inches. 1 kilometer (km)=1000 meters=˜0.6 miles.            1,000,000 microns=1 meter. 1,000 millimeters (mm)=1 meter.            100 centimeters (cm)=1 meter                        micron (μm) one millionth of a meter (0.000001 meter); also referred to as a micrometer.        mil 1/1000 or 0.001 of an inch; 1 mil=25.4 microns.        nanometer (nm) one billionth of a meter (0.000000001 meter).        Angstrom (Å) one tenth of a billionth of a meter. 10 Å=1 nm.            V short for voltage. Different voltages may be applied to different parts of a transistor or memory cell to control its operation.    wafer In microelectronics, a wafer is a thin slice of semiconducting material, such as a silicon crystal, upon which microcircuits are constructed. There are multiple orientation planes in the silicon crystal that can be used. The planes are defined by the “Miller Indices” methodology. Common orientations classified by the “Miller indices” are (100), (011), (110), and (111).